The present invention relates to a data processor for efficiently computing floating point data which is represented to have exponent parts of both variable and fixed lengths.
Floating point data representation is one which is frequently used in scientific and technical computations because it can handle large or small numbers with equal accuracy.
Since, however, the floating point data representation has its exponentially represented part (which will hereafter be referred to as an "exponent part") fixed, it is disadvantages in that its expressable range is limited and that it lacks flexibility to enhance the accuracy of a mantissa even when the exponent has such a small value that it requires very little information.
Therefore, for an example of a method of representing and a system for computing such flexible floating point data as has an exponent part of variable length so that it can express even a remarkably large or small number while representing a numerical value near 1 with high accuracy (Reference should be made to: Reports of Data Processing Association, Vol. 24, No. 2 (in March 1983), entitled "Data Length Independent Real Number Representation Based on Double Exponential Cut II"; and Japanese Patent Laid-Open No. 59-11444, entitled "System for Computing Floating Point Data", and U.S. Pat. application No. 543,426, now U.S. Pat. No. 4,671,641 corresponding to the latter.)
FIG. 2 is a diagram showing an example of the format of a floating point data of 64 bits having an exponent part of fixed length according to the prior art.
In FIG. 2, reference numeral 1 indicates a sign part indicating the sign of a mantissa part 3 to discriminate whether the floating point number is positive or negative. Numerals 4 and 5 indicate an exponent part and the mantissa part, respectively. In case a number x is positive, more specifically, it is represented by EQU x=2.sup.e .multidot.f with an exponent e and a mantissa f.
The sign part 1 is composed of 1 bit; the exponent part is composed of 7 bits and expresses an exponent by using the twos complement; and mantissa part 5 is composed of 56 bits and expresses a mantissa with the twos complement. Here the highest bit of the mantissa part is normally shifted out. The numeral 6 indicates the separation point of the exponent part 4 and the mantissa part 5.
As shown in FIGS. 2 and 3, the floating point representation of the prior art has its separating point 6 of the exponent part 4 and the mantissa part 5 fixed. As a result, the arithmetic of four operations, i.e., the addition, subtraction, multiplication and division in the floating point representation having an exponent part of fixed length of the prior art has the respective number of bits of the exponent part 4 and the mantissa part 5 fixed so that their control is relatively simple.
FIGS. 3A and 3B are diagrams showing the respective formats of examples of the aforementioned floating point data of 64 bits having an exponent part of variable length of the prior art in cases where a later-described parameter m is 0 as well as when it is not 0.
In FIGS. 3A and 3B: numeral 1 indicates a sign part; numeral 6 a separating part; numeral 7 a first (or front half of) exponent part; numeral 8 an exponent part separating part; numeral 9 a second (or rear half of) exponent part; and numeral 10 a mantissa part.
As shown in FIGS. 3A and 3B, in the variable length representation of the exponent part, the total number of the bits of the sign part 1, the exponent parts 7, 8 and 9 and the mantissa part 10 is fixed, but the respective bit lengths of the exponent parts 7, 8 and 9 and the mantissa part 10 are variable in that limited range. In other words, the separating point 6 between the exponent parts 7, 8 and 9 and the mantissa part 10 is movable. As has been described hereinbefore, therefore, the variable length representation of the exponent part can have an enlargement of the range of representable numbers and flexibility in the accuracy representation, but the arithmetic control is more complicated than the case of the fixed length representation of the exponent part.
Since substantially all scientific and technical programs developed in the prior art are based upon data having an exponent part of fixed length, it is necessary that they execute arithmetic of data having an exponent part of not only fixed length but also variable length. In order to satisfy this requirement, there has been applied for patent by the present assignee U.S. patent application No. 666,748, now U.S. Pat. No. 4,675,809, in which is disclosed a data processor having the following problems. Specifically, data having an exponent part of fixed length representation and data having an exponent part of variable length representation are latched in such a form in a floating point register that they are converted into data having a common exponent part of fixed length. In a data processor for multi-programming, therefore, the common data having an exponent part of fixed length representation has to be inversely converted and released in a memory when the content of a floating point register is to be released.
Moreover, the data having an exponent part of fixed length representation are converted into common data having an exponent part of the fixed length representation so that they are enlarged to have an intrinsically unnecessary data width. This is because in the data having an exponent of the variable length representation the exponent part and the mantissa part have variable bit widths so that a rather large data width has to be retained. This raises a problem in that the data width of the exponent part is greatly enlarged to increase the time period for arithmetic processing.
In the description to be made, the exponent part of fixed length representation, the data having an exponent part of fixed length, the exponent part of variable length representation, and the data having an exponent part of variable length will be hereafter be referred to as "fixed length representation", "data having fixed length", "variable length representation" and "data having variable length", respectively.